1. Field of the Invention
The present invention relates to a charge coupled device image sensor and more particularly, to a charge coupled device (hereinafter "CCD") image sensor of an interline transfer type.
2. Description of the Prior Art
Generally, the signal transfer of a charge coupled device (CCD) image sensor may be of three types, a frame transfer type, an interline transfer type, and a frame-interline transfer type.
The CCD image sensor of the frame transfer type has a plurality of photodetectors formed on a plane thereof and a plurality of signal transfer regions formed under the photodetectors. As a result, the CCD image sensor of the frame transfer type may be applied to a system requiring a higher resolution such as broadcasting equipment, or a system of a non-interlaced scanning type such as military equipment.
The CCD image sensor of the interline transfer type has a plurality of photodetectors and a respective plurality of signal transfer regions, formed on a plane thereof. As a result, the CCD image sensor of the interline transfer type may be applied to a commercial system requiring a lower resolution rather than the broadcasting equipment and military equipment, and it may particularly be applied to a television set or a camcorder of an interlaced scanning type. The CCD image sensor of the frame transfer type may also be applied to a commercial system requiring about one million pixels such as a high definition television (HDTV).
In a video cassette recorder (hereinafter "VCR") utilizing the CCD image sensor of the interline transfer type, there have typically been required two hundred and fifty thousand pixels for VHS tape or three hundred and eighty thousand pixels for super VHS tape.
A construction of a conventional CCD image sensor of the interline transfer type will now be described with reference to FIGS. 1A-1D.
With reference to FIG. 1A, there is shown a schematic diagram of a construction of the conventional CCD image sensor of the interline transfer type. The conventional CCD image sensor comprises a N-type horizontal charge coupled device (hereinafter "HCCD") region 3 and a plurality of N-type vertical charge coupled device (hereinafter "VCCD") regions 2, each to which a series of N-type photodiodes 1 are connected. Each of the N-type photodiodes 1 is connected to the N-type VCCD region 2 such that an image signal charge outputted therefrom is transferred to the N-type VCCD region 2 in a single direction. Also, the N-type VCCD regions 2 are connected to the N-type HCCD region 3 such that the signal charges transferred from the photodiodes 1 are transferred to the N-type HCCD region 3 simultaneously in response first to four VCCD clock signals V.phi.1-V.phi.4, each clock signal corresponding to one phase.
Also, at output of the N-type HCCD region 3 are, connected in series, an output gate 4, a floating diffusion region 5, a reset gate electrode 6 and a reset drain 7. In addition, a sensing amplifier 8 is connected to the floating diffusion region 5.
With reference to FIG. 1B, there is shown a layout diagram of the construction of the conventional CCD image sensor in FIG. 1A. The CCD image sensor comprises a channel stop region 9 formed between each of the N-type VCCD regions 2 and each of the corresponding N-type photodiodes 1. An odd gate electrode 10 is formed over each of the N-type VCCD regions 2 and each of the channel stop regions 9 such that it is connected to each of transfer gates 11 of the N-type photodiodes 1 arranged on an odd horizontal line, the odd gate electrode 10 being applied with the first and the second clock signals V.phi.1-V.phi.2. On the other hand, an even gate electrode 12 is formed over each of the channel stop regions 9, each of the N-type VCCD regions 2 and each of the N-type photodiodes 1 such that it is connected to each of transfer gates 13 of the N-type photodiodes 1 arranged on an even horizontal line, the even gate electrode 12 being applied with the third and the fourth clock signals V.phi.3-V.phi.4.
The forming of the odd gate electrode 10 and the even gate electrode 12 may be repeated successively, as they are required, in the same form. Also, these electrodes 10 and 12 are generally electrically isolated from each other by a region (not shown) of an insulating material, such as silicon oxide.
On the other hand, materials of the transfer gates 11 and 13 and the odd and even gate electrodes 10 and 12 may be polysilicons.
The odd gate electrode 10 includes a first odd gate electrode 10a formed under each of the N-type photodiodes 1 on the odd horizontal line and a second odd gate electrode 10b formed over each of the N-type photodiodes 1 on the odd horizontal line and connected to each of the transfer gates 11 of the photodiodes 1 on the odd horizontal line, the first odd gate electrode 10a being applied with the second VCCD clock signal V.phi.2 and the second odd gate electrode 10b being applied with the first VCCD clock signal V.phi.1.
The even gate electrode 12 includes a first even gate electrode 12a formed under each of the N-type photodiodes 1 on the even horizontal line and a second even gate electrode 12b formed over each of the N-type photodiodes 1 on the even horizontal line and connected to each of the transfer gates 13 of the photodiodes 1 on the even horizontal line, the first even gate electrode 12a being applied with the fourth VCCD clock signal V.phi.4 and the second even gate electrode 12b being applied with the third VCCD clock signal V.phi.3.
Also, the first through the fourth VCCD clock signal V.phi.1-V.phi.4 of four phases corresponds to two fields, i.e. an even field and an odd field. The clocking operation of the N-type VCCD region 2 will be described hereinafter in more detail.
With reference to FIG. 1C, there is shown a sectional view, taken along line a--a' in FIG. 1B. The conventional CCD image sensor comprises a N-type substrate 14 and a P type well 15, formed on the N-type substrate 14. Also on the N-type substrate 14 are configured a series of arrangement that the N-type photodiode 1 and the N-type VCCD region 2 on the even horizontal line are connected to each other at a desired interval via the channel stop region 9. Each of the transfer gates 13 is formed over each of the N-type photodiodes 1 and each of the N-type VCCD regions 2 to connect them with each other. Also, over the surface of each of the N-type VCCD regions 2 is formed the second even gate electrode 12b of the even gate electrode 12 being applied with the third VCCD clock signal V.phi.3, to be connected to each of the transfer gates 13 of the N-type photodiodes 1 arranged on the even horizontal line.
The P-type well 15 is comprised of two types, a P-type shallow well 15a and a P-type deep well 15b, for the control of over flow drain (hereinafter "OFD") voltage.
On the surface of each of the N-type photodiodes 1 is generally formed a P.sup.+ -type thin layer 16 for applying an initial bias. As shown in FIG. 1C, the lower side of the channel stop region 9 designated as the character P.sup.+ indicates a P.sup.+ -channel stop ion.
With reference to FIG. 1D, there is shown a sectional view, taken along line b--b' in FIG. 1B. The P-type well 15 is formed on the N-type substrate 14, identically to FIG. 1C. Also, on the N-type substrate 14 are configured a series of arrangement that the N-type photodiode 1 and the N-type VCCD 2 on the even horizontal line are connected to each other at a desired interval via the channel stop region 9. Also, over the surface of each of the N-type VCCD regions 2 is formed the first even gate electrode 12a of the even gate electrode 12 being applied with the fourth VCCD clock signal V.phi.4.
Similarly, on the surface of each of the N-type photodiodes 1 is generally formed P.sup.+ -type thin layer 16 for the applying an initial bias. In FIG. 1D, the lower side of the channel stop region 9 designated as the character P.sup.+ indicates a P.sup.+ -channel stop ion. Herein, the P-type well 15 is comprised of the P-type shallow well 15a and the P-type deep well 15b, for the control of OFD voltage.
The transfer gate 11 of each of the N-type photodiodes 1 arranged on the odd horizontal line is driven only by the first VCCD clock signal V.phi.1 being applied to the second odd gate electrode 10b of the odd gate electrode 10, and the transfer gate 13 of each of the N-type photodiodes 1 arranged on the even horizontal line is driven only by the third VCCD clock signal V.phi.3 being applied to the second even gate electrode 12b of the even gate electrode 12.
The second VCCD clock signal V.phi.2 being applied to the first odd gate electrode 10a of the odd gate electrode 10 and the fourth VCCD clock signal V.phi.4 being applied to the first even gate electrode 12a of the even gate electrode 12 serve merely to transfer image signal charges traveling from the N-type photodiodes 1 arranged on the odd and even horizontal lines toward the HCCD region 3.
The operation of the conventional CCD image sensor of the above-mentioned construction will now be described with reference to FIGS. 2A-2C.
With reference to FIG. 2A, there is shown a timing diagram of the first through fourth VCCD clock signal V.phi.1-V.phi.4 of four phases, each including two fields, an even field and an odd field.
In this drawing, in the odd field of the first VCCD clock signal V.phi.1 being applied to the second odd gate electrode 10b of the odd gate electrode 10 is contained a transfer gate drive voltage V1 of high level (15 V). Also, in the even field of the third VCCD clock signal V3 being applied to the second even gate electrode 12b of the odd gate electrode 12 is contained a transfer gate drive voltage V2 of high level (15 V).
First, when the first through fourth VCCD clock signals V.phi.1-V.phi.4 in the odd field are applied simultaneously, the transfer gates 10 of the N-type photodiodes arranged on each of the odd horizontal lines are turned on simultaneously by the transfer gate drive voltage V1 contained in the first VCCD clock signal V.phi.1.
For this reason, the image signal charges produced from the N-type photodiodes 1 are transferred to the N-type VCCD regions 2 and then toward the N-type HCCD region 3 by the VCCD clocking operation. The image signal charges transferred to the HCCD region 3 are then transferred to the output gate 4 in response to HCCD clock signals H.phi.1 and H.phi.2. The process of the image signal charges being outputted from the HCCD region 3 will be mentioned later in detail.
With reference to FIG. 2B, there is shown a pulse waveform diagram of the first through fourth VCCD clock signals V.phi.1-V.phi.4 at the unit interval K of FIG. 2A. The image signal charges produced from the N-type photodiodes 1 are transferred vertically toward the N-type HCCD region 3 by a series of clocking operation as shown in FIG. 2B.
At this time, the second VCCD clock signal V.phi.2 being applied through the first odd gate electrode 10a of the odd gate electrode 10 formed in the lower side of the odd horizontal line serves merely to transfer the image signal charges transferred from the N-type photodiodes 1 arranged on the even horizontal line by the first VCCD clock signal V.phi.1 to the N-type HCCD region 3, together with the first VCCD clock signal V.phi.1.
Thereafter, if the first through fourth VCCD clock signal V.phi.1-V.phi.4 in the even field as shown in FIG. 2A are applied simultaneously, the transfer gates 13 of the N-type photodiodes 1 arranged on each of the even horizontal lines are turned on simultaneously by the transfer gate drive voltage V2 contained in the third VCCD clock signal V.phi.3.
For this reason, the image signal charges produced from the N-type photodiodes 1 on the even horizontal line are transferred to the N-type VCCD regions 2 and then toward the N-type HCCD region 3 by the VCCD clocking operation as shown in FIG. 2B, in the same manner as that of the odd field.
At this time, the fourth VCCD clock signal V.phi.4 being applied through the first even gate electrode 12a of the even gate electrode 12 formed in the lower side of the even horizontal line serves merely to transfer the image signal charges transferred from the N-type photodiodes 1 arranged on the even horizontal line by the third VCCD clock signal V.phi.3 to the N-type HCCD region 3, together with the third VCCD clock signal V.phi.3.
As stated, the use of the VCCD clock signals of four phases has the effect of transferring the image signal charge in amount more than that of the VCCD clock signals of two phases, i.e., the first and third VCCD clock signal V.phi.1 and V.phi.3.
As a result, as mentioned above, by the VCCD clocking signals of four phases, i.e. the first through fourth VCCD clock signals V.phi.1-V.phi.4 as shown in FIG. 2A, the image signal charges from the N-type photodiodes 1 arranged on the odd horizontal line are first in sequence scanned on the screen through the N-type VCCD regions 2 and then through the N-type HCCD region 3 and then the image signal charges from the N-type photodiodes 1 arranged on the even horizontal line are in sequence scanned on the screen through the N-type VCCD regions 2 and then through the N-type HCCD region 3.
As previously stated, the scanning of the CCD image sensor as mentioned above is usually referred to as the interlaced scanning type.
Referring in detail to FIG. 2C, there is shown a pixel format of one picture, or one frame, the picture being comprised of pixels, each being displayed as the numerals S1 and S2, each designating the image signal charges from the N-type photodiodes 1 arranged on the odd and even horizontal lines as shown in FIG. 1A, respectively.
However, the conventional CCD image sensor of the interline transfer type has a disadvantage, in that it requires a number of clock signals, i.e., a total of seven clock signals, four VCCD clock signals V.phi.1-V.phi.4, two HCCD clock signals H.phi.1 and H.phi.2 and one reset clock signal R.phi., resulting in its high manufacturing cost and complexity. Namely, a system utilizing the CCD image sensor of the interline transfer type has to comprise a signal generator to generate the number of clock signals and a number of its peripheral devices, resulting in its high manufacturing cost and complexity. The CCD image sensor of the interline transfer type may be applied to a system requiring a higher resolution. In a system which does not require the higher resolution, such as, for example, a toy set or a machine-vision system, there is no necessity for necessarily using the CCD image sensor of the interline transfer type. For example, the toy set requires only resolution for recognition of an appearance of an object and the machine-vision system such as a robot system requires only resolution for recognition of a position and a direction of the object.